1. Field of the Invention
This invention relates to electronic systems, and more particularly, to the testing of electronic systems.
2. Description of the Related Art
Digital test equipment is used to test electronic systems, printed circuit assemblies, and integrated circuits in order to detect the presence of various manufacturing defects and to ensure proper operation. During the test process, digital test systems typically drive stimuli to a device under test (DUT) in the form of test vectors. The common values for each bit in a test vector may be either a logic low (i.e. 0), logic high (i.e. 1), or a high impedance (Z). Similarly, digital test systems may commonly be configured to receive data from the DUT in the form of a logic 0, logic 1, or a high impedance value. Other possible test values that may be transmitted and/or received by a test system include intermediate voltages (i.e. between a logic low and a logic high), values with varied timing, and so forth. In general, values that may be transmitted or received include any signal values that may be used to verify the proper functioning of the tested circuitry within voltage, current, and timing requirements.
For test vectors that are driven to the DUT, a digital test system typically utilizes a tri-stateable pin driver. FIG. 1 shows an exemplary test system having a bi-directional channel coupled to a DUT. In the embodiment shown, the test system includes a pattern memory coupled to an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). The ASIC/FPGA is coupled to a driver and a receiver, both of which are coupled to a bi-directional signal line, which in turn is coupled to a DUT. The driver is configured to drive signals to the DUT, while the receiver is configured to receive signals from the DUT. The receiver is also coupled to a comparison circuit in order to allow comparison of received data with expected data. The driver, receiver, and bi-directional signal line may each be one of a number of communication channels used for coupling the test system to the DUT. It is also noted that channels coupled to unidirectional signal lines (with only a driver or receiver coupled thereto) are also possible and contemplated.
The pattern memory for the embodiment shown, as indicated in the table, is configured to store data bits for driving to the test system or comparing with bits received from the test system, driver enable bits, and compare enable bits. Each of these bits in the columns shown is a part of a vector. A group of data bits such as those shown in column A may make up a vector to be driven to the DUT and/or compared with data received from the DUT. The pattern memory may also comprise a drive enable vector that indicates which channels are to be enabled when driving data to the DUT, or a compare enable vector indicating from which channels data received from the DUT is to be compared or monitored. In the table shown in FIG. 1, a logic 1 in the driver enable column (B) indicates that the logic value indicated in the data bit column (A) is to be driven to the DUT. Similarly, a logic 1 in the compare enable column (C) indicates that comparison circuitry is to compare the logic value of a received signal to the value indicated in the data bit column. An “X” in the data bit column indicates that the channel is at a high impedance (‘Hi-Z’) state and no comparison is made (“don't care”).
Since the pattern memory stores a compare enable bit and a drive enable bit for each data bit, the pattern memory for the embodiment shown requires three times the storage than would be required to store the data bits alone. The amount of storage required is even greater when test vectors to be driven to the DUT are different from response vectors to be compared with data received from the DUT, which may be the case. Even in embodiments where the tester is connected to a unidirectional signal node of a DUT, storing an associated enable vector for each data vector requires twice the memory and twice the bus width. Thus, this bandwidth requirement becomes more inefficient and less cost effective in light of the increasing complexity of electronic systems and integrated circuits.